#StayHappening
Wed Oct 07 2026 at 10:00 am to 02:00 pm UTC-07:00

Maximize RISC-V Performance with Custom Design

  • 673 S Milpitas Blvd · Milpitas
  • From USD 0.00
Andes Technology Publisher / Host Andes Technology
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Maximize RISC-V Performance with Custom Design
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Join us in person to unlock top RISC-V speed with personalized chip designs and expert tips!
About this Event

Maximize RISC-V Performance with Custom Design

Join us in person for an exciting opportunity to dive deep into RISC-V performance optimization! Whether you're a developer, engineer, or just a tech enthusiast, this event will show you how to push the boundaries with custom designs that make your RISC-V projects run faster and smarter. Don’t miss out on hands-on experiences and networking with like-minded innovators!


Agenda

🕑: 10:00 AM - 10:30 AM
Check-In
🕑: 10:30 AM - 10:40 AM
Andes: your Commercial-Grade RISC-V Processor IP Partner
Host: Emerson Hsiao

Info: Emerson Hsiao, President of Andes Technology USA, will welcome attendees and provide a brief overview of Andes Technology, including RISC-V market trends, ecosystem collaboration, Andes’ processor IP portfolio and solutions, and customer success stories.


🕑: 10:40 AM - 11:10 AM
Unlocking SoC Performance with RISC-V Custom Instructions
Host: Darren Jones

Info: RISC-V was built for customization. In this talk, Darren Jones will show how to tailor RISC-V to your workloads—boosting SoC performance and efficiency without compromising the standard ISA.


🕑: 11:10 AM - 11:40 AM
Hitting the Memory Wall: CPU Performance Beyond Compute
Host: Mia Chang

Info: The memory wall is the defining bottleneck in today’s AI, automotive, and data center SoCs. In this session, Mia Chang will share real benchmark data on how the Andes AX46-series tackles memory latency from multiple angles, and what it means for your next SoC design.


🕑: 11:40 AM - 12:10 PM
DGEMM Optimization & RISC-V Vector Performance
Host: Trevor Cooper

Info: Trevor Cooper will explore DGEMM optimization on RISC-V, highlighting how the RISC-V Vector (RVV) extension can dramatically improve performance with modest coding effort. The session will cover key optimization techniques, performance considerations, and practical approaches to maximizing vector processing efficiency.


🕑: 12:10 PM - 01:45 PM
Lunch and Networking

Info: Enjoy a complimentary lunch while connecting with Andes experts, speakers, and fellow RISC-V professionals.


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Event venue & nearby stays

673 S Milpitas Blvd, 673 South Milpitas Boulevard, Milpitas, United States

Tickets USD 0.00
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