Name: Rewired for AI: An Introduction to UltraEthernet
Start: 2026-09-08T19:00:00-07:00
End: 2026-09-08T21:00:00-07:00
Location: 925 Thompson Pl

This talk will provide an engineering-first primer on UltraEthernet—the industry’s collaborative answer to modern data center scaling.
About this Event

Join us for Rewired for AI: An Introduction to UltraEthernet, an event on Tue, Sept. 8, 2026 at 7-9pm at Covalent, 925 Thompson Place, Sunnyvale, CA 94085.

We'll have free quality pizza and drinks starting at 6:30pm. Come early and network with our members, other engineers, interested parties, and possible consulting clients.

A Zoom option for this hybrid event is at

https://californiaconsultants.org/event/rewired-for-ai-an-introduction-to-ultraethernet/

NOTE: As in-person registration closes at Noon on Monday, Sept. 7, only the Zoom option is available after that.

Description: As AI and HPC workloads scale exponentially, traditional network fabrics are hitting a critical bottleneck. Legacy Ethernet simply wasn't built for the ultra-low latency and zero-loss tolerances demanded by next-generation clusters. This talk will provide an engineering-first primer on UltraEthernet—the industry’s collaborative answer to modern data center scaling.

Rip Sohan will dissect the architectural gaps of legacy networks, analyze the new data plane building blocks, and unpack the specification’s advanced congestion control and reliability mechanisms. He will also explore how UltraEthernet integrates with existing RDMA ecosystems. Attendees will leave with a definitive mental model of the fabric designed to power the future of compute.

Bio: Rip Sohan is a Fellow Engineer at AMD, where he leads end-to-end system architecture for high-performance enterprise and AI NICs. His work centers on hardware–software co-design across the entire networking stack—spanning NIC micro-architecture, firmware, kernel networking, and user-space acceleration. He specializes in RDMA, multipath transport, and emerging Ultra Ethernet Consortium (UEC) ecosystems.

Prior to AMD, Rip held architectural leadership roles at Xilinx and Solarflare Communications. Earlier in his career, he led a research group at the University of Cambridge focused on reproducible computing systems and low-latency networking. He holds a PhD in Computer Science from the University of Cambridge, with doctoral research spanning operating systems, storage architecture, and endpoint networking.